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Description: VHDL设计——FIFO存储器设计-VHDL design-- FIFO design
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Size: 7168 |
Author: 钱伟康 |
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Description: Hard-decision decoding scheme
Codeword length (n) : 31 symbols.
Message length (k) : 19 symbols.
Error correction capability (t) : 6 symbols
One symbol represents 5 bit.
Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30.
Uses Verilog description with synthesizable RTL modelling.
Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register.
-Hard-decision decoding scheme Codeword l KV (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents five bit. Uses GF (2 ^ 5) with primitive polynomial p (x) = x ^ x ^ 5 2 1 Ge nerator polynomial. g (x) = a ^ a ^ 15* 21 ^ 6 a X* X ^ a ^ 15 2* X ^ a ^ 3 25* X ^ a ^ 4 17 5* X ^ a ^ 18 ^ 6 X* a* X 30 ^ 7 ^ a ^ 20* X ^ a ^ 23 8* X ^ a ^ 9* 27 X 10 ^ a ^ 24* 11 ^ X ^ X 12. Note : a = alpha, primitive element in GF (2 ^ 5) and a ^ i is the root of g (x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizab le RTL modeling. Consists of five main blocks : SC (Syndrome Computation), KES (Key Equation Solver). CSEE (Chien Search and Error Evaluator) Controller and FIFO Register.
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Size: 14336 |
Author: 许茹芸 |
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Description: ddr2 controller, verilog source code from xilinx
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Size: 347136 |
Author: Hubert |
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Description: 同步及异步时序电路fifo源程序及其测试程序.rar - fifo源程序,erilog编写~具有较强的参考价值~ -Synchronous and asynchronous sequential circuits fifo source and test procedures. Rar- fifo source, erilog prepared ~ has a strong reference to the value of ~
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Size: 69632 |
Author: 张勇奇 |
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Description:
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Size: 25600 |
Author: shenyunfei |
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Description: 设计FIFO,使用VERILOG的一篇文章-Design of FIFO, the use of Verilog in an article
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Size: 119808 |
Author: 丁过州 |
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Description: This an USB2.0 chip CY7C68013 Configuraion Example for Slave FIFO mode with "async" mode.
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Size: 123904 |
Author: MyName |
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Description: Synthesizable FIFO Model
This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is 4 and the FIFO width is 32 bits.
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Size: 16384 |
Author: lianlianmao |
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Description:
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Size: 2048 |
Author: dq |
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Description: Generic FIFO, writen in verilog hdl
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Size: 12288 |
Author: marco |
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Description: verilog,异步一进一出的例子,空满的标志。-verilog, into an asynchronous one example, air-filled logo.
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Size: 2048 |
Author: 陈虎 |
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Description: UART16550兼容的串行通讯控制器,Verilog语言描述,采用Altera Cyclone系列芯片实现FPGA综合,因为FIFO部分利用到内部资源实现。已经在某项目中成功应用,特此推出。-UART16550 compatible serial communication controller, Verilog language description, the use of Altera Cyclone series FPGA chip integrated, as part of the use of FIFO to the internal resources to achieve. Projects have been in a successful application, is hereby introduced.
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Size: 10240 |
Author: David.Mr.Liu |
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Description: verilog仿真工具modelsim的使用教程,幻灯片形式的,图文并茂,简单易学.经典的老教材-ModelSim Verilog simulation tool use tutorials, slide the form of illustrations, easy to learn. classic old material
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Size: 505856 |
Author: oasis |
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Description: IA4420的FIFO操作源代码,是c51语言写的,不过移植起来很容易。-IA4420 the FIFO operation source code is written in C51 language, but the transplant is easy.
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Size: 1024 |
Author: 刘先生 |
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Description: FIFO电路Verilog实现
-FIFO circuit realize Verilog
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Size: 3072 |
Author: Jerry |
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Description:
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Size: 2048 |
Author: 李映波 |
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Description:
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Size: 262144 |
Author: Roger |
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Description: 用Verilog语言编写的实现NAND Flash块的控制存取以及同步的FIFO的控制-Using Verilog languages realize NAND Flash block to control access as well as the synchronization FIFO control
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Size: 6144 |
Author: 刘义春 |
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Description: FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输,已验证,直接可用-FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available
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Size: 1028096 |
Author: alison |
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